ECC memory: Error-Correcting Code
ECC memory is RAM that detects and corrects single-bit errors and detects multi-bit errors using extra parity bits. It prevents silent data corruption and crashes from cosmic-ray bit flips, which is why it is standard in servers and required for reliable 24/7 operation.
Standard ECC adds an extra DRAM chip per rank to store check bits, typically using a SECDED scheme that corrects any single-bit error and detects any double-bit error. When a bit flips from radiation or electrical noise, the controller repairs it transparently and logs the event, so the workload keeps running without corrupted data.
Servers extend this with features like Dell SDDC or memory mirroring that survive an entire failed DRAM chip. ECC requires support from both the CPU memory controller and the DIMM, and server RDIMMs and LRDIMMs include it by default. Desktop UDIMMs usually do not.
For any server bought from China that will run production workloads, ECC is not optional. Check that the memory modules are ECC-rated and that the BMC logs correctable errors, which give early warning of a failing DIMM before it causes an outage.
Related
More in Memory
- RDIMM: Registered DIMMAn RDIMM is a server memory module with a register (buffer) between the memory controller and the DRAM chips for address and command signals. Buffering reduces electrical load on the controller, allowing more DIMMs per channel and greater stability than unbuffered UDIMMs.
- LRDIMM: Load-Reduced DIMMAn LRDIMM is a server memory module that buffers both data and address/command signals through an on-module memory buffer. This cuts electrical load further than an RDIMM, enabling the highest per-DIMM capacities and full memory population, at slightly higher latency.
- Memory rank: single / dual / quad rankA memory rank is a 64-bit (72-bit with ECC) block of DRAM chips accessed together by the memory controller. A DIMM can have one, two, or four ranks. Rank count affects capacity, performance through interleaving, and how many DIMMs a channel can support.
- Memory channels & DIMM populationA memory channel is an independent path between the CPU and its DIMMs. Total bandwidth scales with the number of populated channels, so filling every channel matters more than filling every slot. Modern Xeon and EPYC CPUs have 8 or more channels per socket.
- DDR4 vs DDR5 for serversDDR4 server memory runs up to 3200 MT/s and is used by Xeon Scalable 1st–3rd gen and EPYC through Milan. DDR5 starts at 4800 MT/s, reaches 5600 MT/s and higher, and is required by Xeon Sapphire Rapids and later and by EPYC Genoa. The two are not interchangeable.
Need a build that gets this right? Tell us the workload and get an EXW Dalian quote the same business day.
Request a quote