RDIMM: Registered DIMM
An RDIMM is a server memory module with a register (buffer) between the memory controller and the DRAM chips for address and command signals. Buffering reduces electrical load on the controller, allowing more DIMMs per channel and greater stability than unbuffered UDIMMs.
The register on an RDIMM latches address, command, and clock signals before they reach the DRAM chips. This lowers the electrical load the CPU's memory controller sees, so a server can run more modules per channel at high, reliable speeds. Data still flows directly between the controller and the DRAM, so latency overhead is minimal.
RDIMMs almost always include ECC and are the standard choice for mainstream servers using Intel Xeon Scalable and AMD EPYC. They are not electrically compatible with UDIMMs, and a platform is built for one type or the other. Capacities scale from 8 GB up to 64 GB and beyond per module.
When configuring servers from China, match RDIMM speed to what the CPU actually supports, since memory runs at the slower of the module and controller ratings. Populate DIMMs in matched sets across channels, and do not mix RDIMM and LRDIMM in the same server.
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More in Memory
- LRDIMM: Load-Reduced DIMMAn LRDIMM is a server memory module that buffers both data and address/command signals through an on-module memory buffer. This cuts electrical load further than an RDIMM, enabling the highest per-DIMM capacities and full memory population, at slightly higher latency.
- ECC memory: Error-Correcting CodeECC memory is RAM that detects and corrects single-bit errors and detects multi-bit errors using extra parity bits. It prevents silent data corruption and crashes from cosmic-ray bit flips, which is why it is standard in servers and required for reliable 24/7 operation.
- Memory rank: single / dual / quad rankA memory rank is a 64-bit (72-bit with ECC) block of DRAM chips accessed together by the memory controller. A DIMM can have one, two, or four ranks. Rank count affects capacity, performance through interleaving, and how many DIMMs a channel can support.
- Memory channels & DIMM populationA memory channel is an independent path between the CPU and its DIMMs. Total bandwidth scales with the number of populated channels, so filling every channel matters more than filling every slot. Modern Xeon and EPYC CPUs have 8 or more channels per socket.
- DDR4 vs DDR5 for serversDDR4 server memory runs up to 3200 MT/s and is used by Xeon Scalable 1st–3rd gen and EPYC through Milan. DDR5 starts at 4800 MT/s, reaches 5600 MT/s and higher, and is required by Xeon Sapphire Rapids and later and by EPYC Genoa. The two are not interchangeable.
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