Memory rank: single / dual / quad rank
A memory rank is a 64-bit (72-bit with ECC) block of DRAM chips accessed together by the memory controller. A DIMM can have one, two, or four ranks. Rank count affects capacity, performance through interleaving, and how many DIMMs a channel can support.
The controller reads and writes one rank at a time, but it can interleave across multiple ranks to hide latency and keep the bus busy, so dual-rank DIMMs often outperform single-rank at the same capacity. More ranks per DIMM also raise electrical load on the channel, which is why platforms cap the total ranks a channel can drive.
A single-rank DIMM has one rank, dual-rank has two, and quad-rank has four. Rank count combines with chip density to set module capacity. Every platform specifies a maximum ranks-per-channel limit, and exceeding it forces the memory to run slower or prevents full population.
When configuring memory for servers from China, check the CPU's ranks-per-channel budget before filling every slot, especially with quad-rank or LRDIMM modules. Dual-rank RDIMMs are usually the sweet spot for performance per dollar. Keep ranks balanced across channels for even interleaving.
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More in Memory
- RDIMM: Registered DIMMAn RDIMM is a server memory module with a register (buffer) between the memory controller and the DRAM chips for address and command signals. Buffering reduces electrical load on the controller, allowing more DIMMs per channel and greater stability than unbuffered UDIMMs.
- LRDIMM: Load-Reduced DIMMAn LRDIMM is a server memory module that buffers both data and address/command signals through an on-module memory buffer. This cuts electrical load further than an RDIMM, enabling the highest per-DIMM capacities and full memory population, at slightly higher latency.
- ECC memory: Error-Correcting CodeECC memory is RAM that detects and corrects single-bit errors and detects multi-bit errors using extra parity bits. It prevents silent data corruption and crashes from cosmic-ray bit flips, which is why it is standard in servers and required for reliable 24/7 operation.
- Memory channels & DIMM populationA memory channel is an independent path between the CPU and its DIMMs. Total bandwidth scales with the number of populated channels, so filling every channel matters more than filling every slot. Modern Xeon and EPYC CPUs have 8 or more channels per socket.
- DDR4 vs DDR5 for serversDDR4 server memory runs up to 3200 MT/s and is used by Xeon Scalable 1st–3rd gen and EPYC through Milan. DDR5 starts at 4800 MT/s, reaches 5600 MT/s and higher, and is required by Xeon Sapphire Rapids and later and by EPYC Genoa. The two are not interchangeable.
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