DDR4 vs DDR5 for servers
DDR4 server memory runs up to 3200 MT/s and is used by Xeon Scalable 1st–3rd gen and EPYC through Milan. DDR5 starts at 4800 MT/s, reaches 5600 MT/s and higher, and is required by Xeon Sapphire Rapids and later and by EPYC Genoa. The two are not interchangeable.
DDR5 raises bandwidth through higher base speeds and by splitting each module into two independent 32-bit subchannels, which improves access efficiency. It also moves power regulation onto the DIMM and adds on-die ECC inside the chips, separate from the system-level ECC servers still use. DDR4 tops out around 3200 MT/s in servers; DDR5 begins at 4800 MT/s.
The generation is dictated by the CPU platform, not by choice. Intel Cascade Lake supports DDR4-2933, Ice Lake supports DDR4-3200, and Sapphire Rapids moved to DDR5-4800. On AMD, EPYC Rome and Milan use DDR4, while Genoa and Bergamo use DDR5-4800. You cannot fit a DDR5 module in a DDR4 slot or the reverse.
When buying from China, decide the platform first, because it locks your memory generation and pricing. DDR4 systems remain cheaper per gigabyte and are fine for many workloads. Choose DDR5 platforms when you need the extra bandwidth for high core counts, in-memory analytics, or future expansion headroom.
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- RDIMM: Registered DIMMAn RDIMM is a server memory module with a register (buffer) between the memory controller and the DRAM chips for address and command signals. Buffering reduces electrical load on the controller, allowing more DIMMs per channel and greater stability than unbuffered UDIMMs.
- LRDIMM: Load-Reduced DIMMAn LRDIMM is a server memory module that buffers both data and address/command signals through an on-module memory buffer. This cuts electrical load further than an RDIMM, enabling the highest per-DIMM capacities and full memory population, at slightly higher latency.
- ECC memory: Error-Correcting CodeECC memory is RAM that detects and corrects single-bit errors and detects multi-bit errors using extra parity bits. It prevents silent data corruption and crashes from cosmic-ray bit flips, which is why it is standard in servers and required for reliable 24/7 operation.
- Memory rank: single / dual / quad rankA memory rank is a 64-bit (72-bit with ECC) block of DRAM chips accessed together by the memory controller. A DIMM can have one, two, or four ranks. Rank count affects capacity, performance through interleaving, and how many DIMMs a channel can support.
- Memory channels & DIMM populationA memory channel is an independent path between the CPU and its DIMMs. Total bandwidth scales with the number of populated channels, so filling every channel matters more than filling every slot. Modern Xeon and EPYC CPUs have 8 or more channels per socket.
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